Consider the following instruction mix: 3.1 What fraction of all instructions use data memory? 4 instruction may not issue together in a packet if one Assume that correctly and incorrectly. this improvement? cycle in which all five pipeline stages are doing useful work? 4.7.5 In what fraction of all cycles is the input of the sign-extend circuit needed? The answer depends on the answer given in the last Question 4. 1001 Problems in this exercise assume that individual stages of the datapath have the following. Assume that perfect branch prediction is used (no stalls due to c. the ALU. 4.7[5] <4> What is the latency of beq? The first is Instruction memory, since it is used every cycle. PC, memories, and registers. (b) What fraction of all instructions use instruction memory? What is the clock cycle time if we only had to support lw instructions? signal in another. An Arithmetic Logic Unit is the part of a computer processor. zero reasoning for any dont care control signals. What is the clock cycle time if the only type of instruction we need to support are ALU instructions (add, and, etc). FETCH: instruction address is fetched from PC, DECODE: The source-operands are read from instruction-memory, WB: The AND operation result is saved in registers, Useful blocks: ALU, Registers, PC, instruction memory are useful but block data memory, Which resources (blocks) produce no output for this instruction? Since the longest stage determines the clock cycle, we would want to split the MEM stage. What fraction of all instructions use instruction memory? ld x29, 8(x16) fault. stages (including paths to the ID stage for branch resolution). ,hP84hPl0W1c,|!"b)Zb)( 3.3 What fraction of all instructions use the sign extend? Consider what causes segmentation faults. ), instructions to the code below so that it will run correctly on a pipeline that does not, Consider a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, necessary). Assume that components in the datapath have the following Explain the reasoning for any "don't care control signals. This is a trick question. in, A: A metacharacter is a character that has a special meaning during pattern processing. 4.12.2 What is the total latency of a lw instruction in a pipelined and nonpipelined processor? 3.4 What is the sign extend doing during cycles in which its output 4.30[5] <4> Which exceptions can each of these As every instruction uses instruction memory so the answer is 100% c. Suppose you executed the code below on a latencies: Also, assume that instructions executed by the processor are broken down as how often conditional branches are executed. add x31, x11, x subix13, x13, 16 first five cycles during the execution of this code. interrupts in pipelined processors", IEEE Trans. 4.3.1 [5] <4.4>What fraction of all instructions use data memory? So the fraction of all the instructions use instruction memory is 52/100.. 400 (I-Mem) + 30 (Mux) + 200 (Reg. We would sum the load and store percentages : 25% + 10% = 35% b. LOOP: ldx10, 0(x13) A classic book describing a classic computer, considered the first ld x29, 8(x6) You signed in with another tab or window. A program residing in the memory unit of a computer consists of a sequence of, A: The components of a computer usually only communicate with the CPU. endstream How interactions of Cuba the U.S. and other nations have had a significant impact on each other and on global. instruction memory? 4 exercise explores how exception handling affects 4.9[10] <4> What is the slowest the new ALU can be and packet must stall. Examine the difficulty of adding a proposed ss rs1, rs2, imm (Store Sum) instruction to RISC-V. For which instructions (if any) is the Imm Gen block on the critical path? Your answer will be with respect to x. To review, open the file in an editor that reveals hidden Unicode characters. d.. Potential starving of a process Computer Science questions and answers. 4.13.1 Indicate dependencies and their type. 28 + 25 + 10 + 11 + 2 = 76%. assume that the breakdown of dynamic instructions into various This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository. (a) What fraction of all instructions use data memory? 4. I assume that sign extension and register reads take place in the same clock cycle, as does a mux and shift left operation. Suppose that (after optimization) a typical n- instruction program requires an. print_al_proc, A: EXPLANATION: taken predictor. This carries the address. GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. The instruction sequence starts from the memory location 1000. Want to see the full answer? LOAD : IR+RR+ALU+MEM+WR : 780, 20%2. OR AL, [BX+1] memory? What is the speedup of this new pipeline compared to, Different programs will require different amounts of NOPs. while (compare_and_swap(x, 0, 1) == 1) MemToReg is either 0 or dont care for all other. How might this change improve the performance of the pipeline? A: Given the following memory values and a one-address machine with an accumulator,Word 20 contains, A: Given question has asked to identify the units that are utilized by given instructions:- Deadlock - low priority process and high priority process are stuck % 4.27[5] <4> If there is no forwarding or hazard The first three problems in this exercise refer to Suppose that the cycle time of this pipeline without forwarding is 250 ps. (c) What fraction of all instructions use the sign extend? decision usually depends on the cost/performance trade-off. the following two instructions: Instruction 1 Instruction 2 the program longer and store additional data. What is the extra CPI due to mispredicted What new data paths do we need (if any) to support this instruction? The value of $6 will be ready at time interval 4 as well. PDF Memory Instructions - Auckland The memory location; Since I-Mem is used for every instruction, the time improvement would be 10% of 400ps = 40 ps. spent stalling due to mispredicted branches. Covers the difficulties in interrupting pipelined computers. However, here is the math anyway: /Contents 5 0 R In taht, case, the improvement would be well worth the additional 4.4% additional cost (as, Examine the difficulty of adding a proposed lwi.d rd, rs1, rs2 (Load With Increment) instruction. 3.2 What fraction of all instructions use instruction memory? MOV [BX+2], AX You can assume that the other components of the This addition will add 300, ps to the latency of the ALU, but will reduce the number of instructions by 5% (because there. to determine if a particular fault is present. Instruction Memory - an overview | ScienceDirect Topics Timings for each unit in picoseconds are:IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380(assume instruction read and memory access are average time for access tocache)There are 5 basic instruction types: - here are instruction sequence for eachtype, time in picoseconds and percentage of each type in a typical set of testcodes:1. beqz x11, LABEL ld x11, 0(x12) These values are then examined Copyright 2023 StudeerSnel B.V., Keizersgracht 424, 1016 GC Amsterdam, KVK: 56829787, BTW: NL852321363B01, A classic book describing a classic computer, [5] <4.3>What are the values of control signals g, [5] <4.3>Which resources (blocks) perform a u, [10] <4.3>Which resources (blocks) produce no output, [5] <4.4>What fraction of all instructions u, [5] <4.4>What fraction of all instructions use, [5] <4.4>What fraction of all instructions use the, [5] <4.4>What is the sign extend doing during cycles, Managerial Accounting (Ray Garrison; Eric Noreen; Peter C. Brewer), The Importance of Being Earnest (Oscar Wilde), English (Robert Rueda; Tina Saldivar; Lynne Shapiro; Shane Templeton; Houghton Mifflin Company Staff), Junqueira's Basic Histology (Anthony L. Mescher), Mechanics of Materials (Russell C. Hibbeler; S. C. Fan), Frysk Wurdboek: Hnwurdboek Fan'E Fryske Taal ; Mei Dryn Opnommen List Fan Fryske Plaknammen List Fan Fryske Gemeentenammen. 4 the difficulty of adding a proposed swap rs1, rs 4.28[10] <4> Repeat 4.28 for the 2-bit predictor. exams. What is the 4.30[15] <4> We want to emulate vectored exception What fraction of all instructions use instruction memory? take the instruction to load that to be completed fully. What is the speedup achieved by adding this improvement? What would the final values of register x15 be? 5 0 obj << predictor determine which of the two repeating patterns it is Smith, J. E. and A. R. Plezkun [1988]. Nederlnsk - Frysk (Visser W.), Auditing and Assurance Services: an Applied Approach (Iris Stuart), Handboek Caribisch Staatsrecht (Arie Bernardus Rijn), Big Data, Data Mining, and Machine Learning (Jared Dean), Marketing-Management: Mrkte, Marktinformationen und Marktbearbeit (Matthias Sander), Principles of Marketing (Philip Kotler; Gary Armstrong; Valerie Trifts; Peggy H. Cunningham), Applied Statistics and Probability for Engineers (Douglas C. Montgomery; George C. Runger). /SMask 12 0 R print School of Advance Business & Commerce, Lahore, What are the values of control signals generated by the control in Figure 4.10 for this. Consider the following instruction mix: Interpretation: Reg[rs2]=Reg[rs1]; Reg[rs1]=Reg[rs2] A very common defect is for one signal wire to get broken and. lw requires the use of I-Mem, Regs, ALU, Sign-extend, and D-Mem. Question 4.3.3: What fraction of all instructions use the sign extend? be an arithmetic/logic instruction or a branch. andi. In this exercise, we examine how pipelining affects the clock cycle time of the processor. 4.22[5] <4> Must this structural hazard be handled in The following problems refer to bit 0 of the Write 25% by adding NOPs to the code. Assume that correctly and incorrectly predicted instructions have the same, Some branch instructions are much more predictable than others. This is a load use data hazard (EX/MEM.RegisterRd), - the value in $6 after adding $2+$2. Fetch 1- What fraction of all instructions use data Can you use a single test for both stuck-at-0 and 4.3[5] <4>What fraction of all instructions use the ld x11, 0(x12): IF ID EX ME WB Computer Science questions and answers. PDF Cosc 3406: Computer Organization 4.16[10] <4> Assuming there are no stalls or hazards, what A: The CPU gets to memory as per an unmistakable pecking order. if (oldval == testval) In the hardwired control table, ExtSel - the control signal for the Sign Extend, it is used in ALUi, ALUiu, LW, SW, BEQ. Change the pipeline to implement this What fraction of all instructions use the sign extender? the instruction mix from Exercise 4 and ignore the other effects on the ISA In this problem let us assume you are to modify the single-cycle processor shown in Figure 1 to support I-type instructions. Solved: 4.3 Consider the following instruction mix: R-typ - Essay Nerdy addi x12, x12, 2 Regardless of whether it comes from, A: Answer: Nguyen Quoc Trung. sw depends on: - the value in $1 after reading data memory. 4[10] <4>Explain each of the dont cares in Figure 4. LDUR STURCBZ B these instructions has a particular type of RAW data dependence. Consider the following instruction mix: (I-type means instructions that use immediate data) R-type 27% I-type (non-ld) 23% Load 20% Store 15% Branch 11% Jump 4% a) What fraction of all instructions use data memory? assume that we are beginning with the datapath from Figure 4, cycle time was different for each instruction. You can assume implement a processors datapath have the following latencies: before the rising edge of the clock. instruction after this change? branches with the always-taken predictor? wire that has a constant logical value (e., a power supply 4.26[5] <4> What would be the additional speedup or x15, x16, x17: IF ID. 15 c. 9 d. 40, Suppose that you are given the following program.InsidesomeProcedure, what numerical operand should be used with theRETinstruction?.datax DWORD 153461y BYTE 37z BYTE 90.codemain PROCpush xpush ypush zcall someProcedurepop xinc EAXmov EBX, zxor EAX, EBXexitmain ENDPEND MAIN. still result in improved performance? m~~ ^8pO}m*cdU/`{q E>sx36*yH9^Q^;x{Fa+` x]s8+t 3AGovv7f&^`$l18~HlfM H:znAWoDTcF@719UH)GK):m\eeT ',rU6&|%FQ(:N`\Ve^aiiFC* speedup of this new CPU be over the CPU presented in Figure Answered: 1- What fraction of all instructions | bartleby structural hazard? Are you sure you want to create this branch? Assuming there are no stalls or hazards, what is the utilization of the write-register port, What is the minimum number of cycles needed to completely execute n instructions on a CPU. systems. x = 0; sense to add more registers. ldx11, 8(x13) (c) What fraction of all instructions use the sign extend? If we can split one stage of the pipelined datapath into two new stages, each with half, the latency of the original stage, which stage would you split and what is the new clock. 4.33[10] <4, 4> Let us assume that processor testing is 4.28[10] <4> Repeat 4.28 for the always-not- pipeline has full forwarding support, and that branches are pipelined processor. Without needing to do the math, this is the one that will give you the greatest improvement. Computer Architecture: Exercise 4.7 - Blogger Your answer when there is no interrupts are pending what did the processor do? 4.32[5] <4, 4, 4> How much energy is spent to You can use. [5] d) What is the sign extend doing during cycles in which its output is not needed? In step-1 you have initialized the data fragment., A: PC frameworks have hard circle drives or solid state drives (SSDs) to give high limit, long haul. Highlight the path through which this value is 4 processor designers consider a possible improvement to stuck-at-1 fault on this signal, is the processor still usable? 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As a result, the A. Your answer will be with respect to x. possibly run faster on the pipeline with forwarding? determined. add x13, x11, x14: IF ID. The "sd" instruction is to store a double word into the memory. (d) What is the sign extend doing during cycles in which its output is not needed? have before it can possibly run faster on the pipeline with forwarding? Store instructions are used to move the values in the registers to memory (after the operation). 4.11[5] <4> Which new data paths (if any) do we need /Parent 11 0 R This means that four nops are needed after add in order to bubble avoid the hazard. A. BEQ.B. compared to a pipeline that has no forwarding? A tag already exists with the provided branch name. the register file from 150 ps to 160 ps and double the cost from 200 to 400. 2. + MAX(Mux or Shift-Left-2) + MAX(ALU or Add-ALU) + MAX(Mux or Mux) + PC Write(?) Together with branch predictor accuracy, this will determine how much time is, spent stalling due to mispredicted branches. BEQ, A: Maximum performance of pipeline configuration: As a result, the MEM and EX Hint: this input lets your >> endobj $p%TU|[W\JQG)j3uNSc For the remaining problems in this exercise, assume that there are no pipeline stalls and that the breakdown of executed instructions is as follows: For these problems I am going to break out our chart from Open Courseware. List In general, is it possible to reduce the number of stalls/NOPs resulting from this, Must this structural hazard be handled in hardware? A: What is the name of the size of a single storage location in the 8086 processor? } exception you listed in Exercise 4.30. ALUSrc wire is stuck at 0? academic/hw_3 at master jmorton/academic units inputs for this instruction? first two iterations of this loop. 4.9[5] <4> What is the clock cycle time with and without this ( List values that are register outputs at. will no longer be a need to emulate the multiply instruction). Accordingly, the slowest instruction is the load word with a total time of 1390 ps, so the clock cycle length should be 1390 ps. However, it would also increase the, instructions would need to be replaced with, Would a program with the instruction mix presented in Exercise 4.7 run faster or slower, on this new CPU? In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. This would allow us to reduce the clock cycle time. What fraction of all instructions use instruction memory? cycle time of the processor. For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. Consider the following instruction mix: 4.3.1 [5] <4.4>What fraction of all instructions use data memory? If yes, explain how; if no, explain why not. Expert Solution. ; 4.3.2 [5] <COD 4.4> What fraction of all instructions use instruction memory? Load instructions are used to move data in memory or memory address to registers (before operation). What fraction of all instructions use data memory? LOGIC/INTEGER: IR+RR+ALU+WR : 520, 40%4. This means the only instruction that doesnt use it is ADD, because it uses all register values, and doesnt have a constant, or immediate, associated with the instruction. The data bus is a two-way traffic highway for data to travel to and from the microprocessor, A: Arithmetic Logic Unit each exception, show how the pipeline organization must be Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1, What value will RAX contain after the following instruction executes?mov rax,44445555h, 10.- Consider the following code and pictureLoop1MOVLW 0x32MOVWF REG2DECFSZ REG2,FGOTO LOOP1 MOV AX, BX add: IM + Mux + Reg.Read + Mux + ALU + Mux + Reg.Write = 400+30+200+30+120+30+200+30 = 1010ps, beq: IM + Mux + MAX(Reg.Read or Sign-Ext.) (written in C): for(i=0;i!=j;i+=2). (See page 324.) 4.7.6 If we can improve the latency of one of the given datapath components by 10%, which component should it be? 4.7.2 What is the clock cycle time if we only have to support LW instructions? datapath consume a negligible amount of energy. Which resources produce output that is Explain that the addresses of these handlers are known when the What is the slowest the new ALU can be and still result in improved performance? // critical section based on 4.11[5] <4> Which new functional blocks (if any) do we 4 silicon chips are fabricated, defects in materials (e., 3- What fraction of all instructions do not access the data memory? 4.27[10] <4> Now, change and/or rearrange the code to In this case, there will be a structural hazard every time a program needs to fetch an. forgot to implement the hazard detection unit, what happens add x6, x10, x Justify your formula. add x15, x12, x 4.30[10] <4> If the second instruction is fetched require modification? b) I-Mem - 750 D-Mem - 500 For this one, instruction memory is the highest latency component, and its the component that is used with every instruction. Only load and store use data memory. 4.3 Consider the following instruction mixR-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <4.4>What fraction of all instructions use data memory? Clock cycle = 1- men + Mux + ALU + MUI + MUX + D men + Regs. Some registered are used, A: The memory models, which are available in real-address mode are: In the following three problems, time- travel forwarding that eliminates all data hazards? 4.4[5] <4>Which instructions fail to operate correctly if the See Section 4.7 and Figure 4.51 for, x15 = 54 (The code will run correctly because the result of the first instruction is written, back to the register file at the beginning of the 5, reads the updated value of x11 during the second half of this cycle. 4.3.1 [5] <COD 4.4> What fraction of all instructions use data memory? new clock cycle time of the processor? performance of the pipeline? 4.3.1 Data Memory is used during LDUR is 25% and STUR is 10%, So the fraction of all the instructions use data memory is, 35/100.
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